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1 mx23l1654 16m-bit low voltage, serial mask rom with 50mhz spi bus interface key features ? operating voltage ranges from 3.0v to 3.6v serial peripferal interface compatible-mode 0 and 3 high performance : "fast read" mode at 50mhz and "normal read" at 20mhz low power consumption : 8ma for fast read mode or 4ma for normal read mode low standby current : 15ua general description the mx23l1654 is a 16mbit (2m bytes) serial mask rom accessed by a high speed serial peripheral interface. pin configurations symbol description sclk serial clock si serial data input so serial data output cs# chip select hold# hold to pause the device without deselecting the device vcc power supply vss ground pin description 16-pin sop (300 mil) note: 1. nc=no connection 2. see page 15 for package dimensions, and how to identify pin-1. p/n: pm1247 rev. 1.5, nov. 09, 2007 1 2 3 4 5 6 7 8 hold# vcc nc nc nc nc cs# so 16 15 14 13 12 11 10 9 sclk si nc nc nc nc vss nc order information part no. s peed package remark MX23L1654MC-20G 20ns 16-sop pb-free
2 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 memory organization the memory is organized as: - 2m bytes block diagram address generator memory array y-decoder x-decoder data register si sclk clock generator state machine mode logic sense amplifier output buffer so cs# hold#
3 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 figure 1. spi modes supported sclk msb cpha shift in shift out si 0 1 cpol 0 (spi mode 0) (spi mode 3) 1 so sclk msb note: cpol indicates clock polarity of spi master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which spi mode is supported. device operation stand-by mode when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps in standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. active mode when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. spi feature input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of spi mode 0 and mode 3 is shown as figure 1.
4 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 hold# cs# sclk hold condition (standard) hold condition (non-standard) the serial data output (so) is a high impedance, that both serial data input (si) and serial clock (sclk) are "don't care" during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start the communication with chip, the hold# must be kept as high and cs# must be kept as low. figure 2. hold condition operation hold feature hold# pin signal goes low to hold any serial communications with the device. the operation of hold requires chip select(cs#) to stay low and starts on falling edge of hold# pin signal while serial clock (sclk) signal keeps to be low (if serial clock signal does not keep to be low, hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while serial clock(sclk) signal keeps to be low( if serial clock signal does not keep to be low, hold operation will not end until serial clock being low), please refer to figure 2.
5 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 table 1. command definition notes: 1. n bytes are read out until cs# goes high. 2. it is not recommended to adopt any code not in the above command definition table. command 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte set code rdid 9fh manufacturer memory type memory (read id) id id density id read 03h ad1 ad2 ad3 data out note 1 (read data) (a23-a16) (a15-a8) (a7-a0) (d7-d0) fast read 0bh ad1 ad2 ad3 dummy data out (fast read data) (a23-a16) (a15-a8) (a7-a0) cycle (d7-d0)
6 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 command description (1) read identification (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and is followed by device id of 2-byte. the mxic manufacturer id is c2h, the memory type id is 05h as the first-byte device id, and the individual device id of second-byte id is:15h. the sequence of issuing rdid instruction is: cs# goes low-> sending rdid instruction code -> 24-bits id data is sent out on so -> to end rdid operation which can use cs# to be high at any time during data out. (see figure 3) when cs# goes high, the device is at standby stage. table of id definitions: rdid manufacturer id memory type memory density 9fh c2h 05h 15h (2) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low-> sending read instruction code-> 3-byte address is sent on si -> data out on so-> to end read operation which can use cs# to be high at any time during data out. (see figure 4) (3) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the first address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low-> send fast_read instruction code-> 3-byte address is sent on si-> 1-dummy byte address is sent on si->data out on so-> to end fast_read operation which can use cs# to be high at any time during data out. (see figure 5) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle.
7 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 figure 3. read identification (rdid) sequence (command 9f) 2 1 3456789101112131415 command 0 manufacturer identification high-z msb 15 1413 3210 device identification msb 765 3210 16 17 18 28 29 30 31 sclk si cs# so 9f figure 4. read data bytes (read) sequence (command 03) sclk si cs# so 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command
8 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 figure 5. read at higher speed (fast_read) sequence (command 0b) 23 2 1 345678910 28293031 2221 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so 0b command
9 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 notice: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage of the device. this is stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions in long period of time may affect reliability. 2. specifications contained within the following table 2 and 3 are subjects to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see figure 3,4. rating value ambient operating temperature 0 c to 70 c storage temperature -65 c to 150 c applied input voltage -0.6v to 4.0v applied output voltage -0.6v to 4.0v vcc to ground potential -0.6v to 4.0v absolute maximum ratings electrical specifications capacitance ta = 25 c, f = 20 mhz symbol parameter min. typ max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v figure 6.maximum negative overshoot waveform figure 7. maximum positive overshoot waveform vss vss - 2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns
10 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 figure 8. input test waveforms and measurement level figure 9. output loading ac measurement level input timing referance level output timing referance level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: the rise and fall time of input pulse < 5ns device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v the condition "cl=30pf" includes jig capacitance
11 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 symbol parameter notes min. typ max. units test conditions isb1 vcc standby 1 15 ua vin = vcc or gnd current cs# = vcc icc1 vcc read 1 8 ma f=50mhz sclk=0.1vcc/0.9vcc, so=open 4 ma f=20mhz sclk=0.1vcc/0.9vcc, so=open ili input load 1 2 ua vcc = vcc max current vin = vcc or gnd ilo output leakage 1 2 ua vcc = vcc max current vin = vcc or gnd vil input low voltage -0.5 0.3vcc v vol output low voltage 0.4 v iol = 1.6ma vih input high voltage 0.7vcc vcc+0.4 v voh output high voltage vcc-0.2 v ioh = -100ua table 2. dc characteristics (temperature = 0 c to 70 c, vcc = 3.0v ~ 3.6v)
12 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 table 3. ac characteristics (temperature = 0 c to 70 c, vcc = 3.0v ~ 3.6v) symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for fast_read, rdid d.c. 50 mhz commands (condition:30pf) frsclk fr clock frequency for read commands d.c. 20 mhz tch(1) tclh clock high time 9 ns tcl(1) tcll clock low time 9 ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 5 ns tshsl tcsh cs# deselect time 100 ns tshqz(2) tdis output disable time 8 ns tclqv tv clock low to output valid 8 ns tclqx tho output hold time 0 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns thhqx(2) tlz hold to output low-z 8 ns thlqz(2) thz hold# to output high-z 8 ns thlch hold# setup time (relative to sclk) 5 ns tchhh hold# hold time (relative to sclk) 5 ns thhch hold setup time (relative to sclk) 5 ns tchhl hold hold time (relative to sclk) 5 ns notes: (1). tch + tcl must be greater than or equal to 1/ fc (2). the values in the table are guaranteed by characterization, not 100% tested in production. (3). indicated as a slew rate.
13 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 figure 10. input timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 11. output timing lsb addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv sclk so cs# si
14 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 figure 12. hold timing tchhl thlch thhch tchhh thhqx thlqz sclk so cs# hold# * si is "don't care" during hold operation.
15 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 package information
16 p/n: pm1247 rev. 1.5, nov. 09, 2007 mx23l1654 revision history revision description page date 1.1 1. changed part name from mx23l1654a to mx23l1654 all sep/23/2005 2. modified figure 2. read identification (rdid) instruction sequence p7 and data-out sequence 1.2 1. modified table 9. ac characteristics p14 nov/03/2005 1.3 1. modified supply voltage from 2.7~3.6v to 3.0~3.6v p1,12 dec/05/2005 1.4 1. added statement p19 nov/07/2006 1.5 1. tightened maximum standby current from 50ua to 15ua p1,11 nov/09/2007 2. changed format arrangement all
mx23l1654 m acronix i nternational c o., l td . headquarters macronix, int'l co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 email: sales.northamerica@macronix.com macronix japan cayman islands ltd. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. taipei office macronix, int'l co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 singapore office macronix pte. ltd. 1 marine parade central #11-03 parkway centre singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096

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